FIG. 1 is a schematic view of an active matrix liquid crystal display. As is well-know, an AMLCD comprises a liquid crystal layer in which a plurality of independently addressable pixels Pij are defined, for example by a patterned electrode. The pixels Pij are generally arranged in a matrix of rows and columns, as shown in FIG. 1. The pixel matrix in FIG. 1 has m pixel columns and n pixel rows. Each pixel contains a portion Dij of the liquid crystal layer of the AMLCD, connected to a switching element Tij which may be, for example, a thin film transistor. The gates of all TFTs within a row j of pixels are connected to a gate line Gj, and each gate line is connected to a gate driver 1. The sources of all TFTs within a column i of pixels are connected to a source line Si, and each source line is connected to a source driver 2. Image data for display is input to the source driver 2, for example over video lines.
In a typical display-driving scheme, the gate driver 1 selects a row of pixels by driving one gate line Gj to be “high” thereby to turn on all the TFTs whose gates are connected to that gate line, and keeping all other gate lines “low”. The source driver 2 samples input image data, and outputs corresponding voltages to each of the source lines. The voltage output on a particular source line is coupled to the pixel that is in the column of pixels connected to that source line and that is connected to the gate line Gj which is being driven “high” by the gate driver.
Once the image data for a row of pixels has been sampled by the source driver and the source driver has output corresponding voltages to each source line, the gate driver selects the next row of pixels by driving another gate line, usually the next gate line Gj+1, “high” and keeping all other gate lines “low”, and the above process is repeated. Usually, an image is displayed by selecting pixels from left to right and from top to bottom.
Each pixel Pij may comprise a capacitor Cij connected in parallel with the liquid crystal element Dij, for stabilising the voltage maintained across the liquid crystal element Dij while the TFT Tij is off between two successive operations of addressing that pixel.
In a full colour AMLCD, each pixel within the pixel matrix may typically consist of a red segment, a green segment and a blue segment. Each segment corresponds generally to the pixel Pij shown in FIG. 1, and each segment contains a TFT to control the voltage applied across the part of the liquid crystal layer in that segment. Thus, in a full-colour AMLCD there are three source lines for each one column of pixels.
A typical source driver is shown in FIG. 2. The source driver 2 contains a shift register 3, a level shifter 4 comprising a plurality of level shifter circuits 4i (where i=0, 1, 2 . . . (m−1)), and a sampler 5 comprising a plurality of sampling circuits 5i (where i=0, 1, 2 . . . (m−1)). The shift register 3 is connected to first and second voltage supply lines 7, 8 which provide first and second supply voltages VDD, VSS respectively. The sampler 5 has input data lines 9 for receiving an input data signal that defines a image to be displayed on the AMLCD; the input data lines 9 may be video lines and the input data signal may be a video signal. Each sampling circuit 5i provides, in dependence on the input data signal, an output signal that is fed to the source line Si connected to the transistors Tij of the ith column of pixels. (FIG. 2 shows a source driver for a full-colour display, so that each sampling circuit 5i in fact provides three output signals for a column of pixels, one for the red segment of the pixel being addressed, one for the green segment of the pixel, and one for the blue segment of the pixel; a source driver for a mono-chromatic display would provide only a single output signal for a column of pixels.)
FIG. 2 illustrates a single phase source driver, which provides an output signal to only one column of pixels at a time. In a first time period, the first output SR0 of the shift register is high and all other outputs SR1 . . . SR(m−1) are low, so that only the sampling switches 6 in the first sampling circuit 50 are actuated (i.e., closed) to provide an output signal from the sampling circuit 50. In the next time period the second output SR1 of the shift register is high and all other outputs SR0 and SR2 . . . SR(m−1) are low, so that only the second sampling circuit 51 is actuated to provide an output signal, and so on. This is shown in FIGS. 3(a)-3(h), which illustrate the operation of a single phase source driver. FIG. 3(a) illustrates the first time period in which SR0 is high and all other outputs of the shift register 3 are low, FIG. 3(b) illustrates the second time period in which SR1 is high and all other outputs of the shift register 3 are low, FIG. 3(c) illustrates the penultimate time period in which the penultimate output SR(m−2) is high and all other outputs of the shift register 3 are low, and FIG. 3(d) illustrates the final time period in which the last output SR(m−1) is high and all other outputs of the shift register 3 are low. The full line in FIGS. 3(a) to 3(d) represents the ith output SRi from the shift register, the dotted line labelled VSHIFTin represents suitable input voltages to the ith sampling circuit of the sampler 5 for driving the gate of an n-type TFT, and the broken line labelled VSHIFTip represents suitable input voltages to the ith sampling circuit of the sampler 5 for driving the gate of a p-type TFT. The bounds of the signals SRi are the voltages VSS and VDD shown in FIG. 2. The bounds of the VSHIFT signals are the voltages VSSH and VDDH shown in FIG. 2. FIGS. 3(e) to 3(h) each represent the source lines of a column of pixels, and show the data transitions on the source lines as a row of image data is sampled. The transitions in FIG. 3(e) are triggered by the first output SR0 of the shift register shown in FIG. 3(a), the transitions in FIG. 3(f) are triggered by the output SR1 of the shift register shown in FIG. 3(b), the transitions in FIG. 3(g) are triggered by the output SR(m−2) of the shift register shown in FIG. 3(a), and the transitions in FIG. 3(h) are triggered by the output SR(m−1) of the shift register shown in FIG. 3(d).
In addition to single phase source drivers, multi-phase source drivers are also known. In a multi-phase source driver the image data are sampled N columns at a time, where N (an integer) is the phase of the system.
The sampling switches 6 in the sampling circuits 5i are typically TFT analogue switches. In principle, the gates of the sampling switches 6 could be driven directly by the output signals SRi from the shift register 3. However, it is often desirable to drive the gates of the sampling switches at a voltage that is higher than the upper voltage level output by the shift register (in the case of an n-type TFT as a sampling switch), or at a voltage that is lower than the lower voltage level output by the shift register (in the case of a p-type TFT as a sampling switch). An increase in the gate-source voltage applied across an n-type TFT sampling switch 6, or a decrease in the gate-source voltage applied across a p-type TFT sampling switch 6, allows the area of the TFT to be reduced accordingly, so reducing the physical size of the source driver. Moreover, smaller sampling switches reduce the capacitive loading of the video lines 9, thereby reducing the dynamic power consumed by the source driver.
It is therefore known to provide the level shifter 4 between the shift register 3 and the sampler 5, to increase the “swing” of the output of the shift register (i.e., to increase the difference between the upper and lower limits of the shift register output). FIG. 2 shows a typical prior art source driver, in which the level shifter operates from additional voltage power supply rails that provide voltages VDDH, VSSH, where VDDH>VDD and VSSH<VSS (it is assumed that VDD>VSS), and increase the swing of the shift register signals to these levels. That is, the level shifter 4 can output a voltage as great as VDDH or as low as VSSH, whereas the shift register can output a voltage only as great as VDD or only as low as VSS. However, the need to provide the additional voltages sources VDDH, VSSH complicates the source driver. Moreover, the saving in power consumption arising from a reduction in the size of the TFT switches 6 may be offset by the increased power consumption of the level shifters and any associated buffer circuits.
Typical level shifter circuits are shown in FIG. 4. When the input voltage to the upper half of the circuit is “low” the transistor 37 is off, but the transistor 39 is on since the output of the inverter 38 is “high” so that the output 40 of the upper half of the circuit is connected to the VSS supply line. When the input voltage to the upper half of the circuit goes “high” the transistor 37 switches on and connects node 41 to the VSS supply line and so applies a voltage VSS to the gate of the p-transistor 43. This turns the transistor 43 on, thereby connecting the output 40 of the upper half of the circuit to the VDDH supply line. At the same time the p-transistor 42 is switched off so as to isolate the node 41 from the VDDH supply line. Thus, the upper part of the circuit of FIG. 4 can provide an output voltage greater than VDD; the lower part of the circuit can similarly provide an output voltage lower than VSS. These circuits may be cascaded to generate the waveforms shown in FIGS. 3(a) to 3(h), or may be used separately to generate the waveforms shown in FIGS. 5(a) to 5(h). The waveforms shown in FIGS. 5(a) to 5(h) correspond to the waveforms shown in FIGS. 3(a) to 3(h) respectively. The bounds of the VSHIFTn signals in FIGS. 5(a) to 5(d) are the voltages VDDH and VSS shown in FIG. 2, and the bounds of the VSHIFTp signals in FIGS. 5(a) to 5(d) are the voltages VDD and VSSH shown in FIG. 2.
There are a number of prior art documents which describe a source driver of the general type shown in FIG. 2 having a level shifter interposed between the shift register and the sampler. In general, these prior art source drivers suffer from the requirement to provide additional high voltage power supply rails and control lines for the level shifters. The high voltage rails in particular can significantly increase the power consumption of the level shifters and any buffering using these rails.
U.S. Pat. No. 6,765,552 describes a display device with a stage of level shifters 4 (denoted as “LS”) between a shift register 3 and a sampling circuit 5, as shown in FIG. 6. However, the level shifters require a separate power supply voltage.
US patent application No. 2005/0012887 describes a display device with level shifters 4 operating from a separate power supply, as shown in FIG. 6. The device uses TFTs of a single type (either n-type or p-type).
US patent application No. 2004/0109526 describes a single-type shift register with built-in level shifters (denoted as “LS”) operating from a separate power supply. The level shifters also require additional clocking signals.
U.S. Pat. No. 6,483,889 describes a shift register with level shifters operated from a separate power supply. This document provides the basis for the display device of US patent application No. 2005/0012887.
U.S. Pat. No. 5,105,187 describes a shift register with internal voltage boosting. The voltage boosting eliminates the need to provide additional voltage supply rails but requires additional boost control lines.
U.S. Pat. No. 5,061,920 describes a source driving scheme which uses level shifters to shift the logical level of the data to a switching level, implying the use of conventional level shifters.
US 2005/0030276 describes a shift register including control circuits corresponding to respective blocks. A level shifter of the next stage is controlled by one of the outputs of the shift register and one of the outputs of a series of flip-flop circuits. The level shifter operates only for the minimum period required to output the shifted output from the current block, thereby reducing the power consumption.